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SONY STRDA30ES
Owner's Manual


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  • PDF Format
  • Complete manual
  • Language: English
Price: $4.99

Description of SONY STRDA30ES Owner's Manual

Complete owner's manual in digital format. The manual will be available for download as PDF file after You purchase it.

Owner's Manual ( sometimes referred to as User's Guide or User's Manual ) contains information on how to use Your device. After placing order we'll send You download instructions on Your email address.

The manual is available in languages: English

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Text excerpt from page 35 (click to view)
4-26. IC BLOCK DIAGRAMS
IC1101 CXD8495AQ (DIGITAL BOARD)

36

35

34

33

32

31

30

29

28

27

26

25

TIMING GENERATOR LD/DQSY 37 SRDT 38 D0

X' TAL OSC 24 D GND 23 SBCK CD SUB-CODE EMOE, SCDOUT, DETECTION GPIO11 PSEL, 10 TEST2 X OUT EXTMEM, 11 12 D VDD R/W, SCDIO, MODE X IN GPIO10 MUTING OUTPUT 22 SFSY 21 PW 20 SBSY 19 D VDD

39

MICRO COMPUTER MULTI PLEXER

DI/SWDT 40 CE/XLAT 41 CL/SCLK 42 D VDD 43 DIN1 44 DIN2 45 DIN3 46 DIN4 47 DGND 48

INTERFACE AUDATA2 DOUT/V LRCK

ERROR LOCK DETECTION

EMPHA DATA OUT RC1 BCLK

18 VCO RC2 SUB 2 17 V IN

DATA DEMODULATOR

SCLKN2 CCB/SUB SUB 1

16 A GND

CMPDAT, SDATAN2 D GND

15 R CLKMD ERROR LRCKN1 14 A VDD

STCCLK2 CLK OUT2

13 N.C.

XMT958 VDD3
1 2 3 4 5 6 7 8 9

TEST

IC1106 CS4926 (DIGITAL BOARD)
DS, SDATAN1 VSS1 SCLKN1, RCV958, GPIO9
20 19

28 CMPREQ,LRCKN2 CLK IN CLKSEL FILTD FILTS VDDA VSSA 29 30 31 32 33 34 35 RAM INPUT BUFFER PLL CLOCK MANAGER

27

26 25 24 23 22

VSS3 TEST1 CLK OUT1

21

18

COMPRESSED DATA INPUT INTERFACE SP DIF RECEIVER

DIGITAL AUDIO INPUT INTERFACE

SCDIN CS
17 DATA0,EMAD0,GPIO0 FRAMER SHIFTER INPUT BUFFER CONTROLLER PARALLEL or SERIAL 16 DATA1,EMAD1,GPIO1 15 DATA2,EMAD2,GPIO2 14 DATA3,EMAD3,GPIO3 13 VSS2 12 VDD2 11 DATA4,EMAD4,GPIO4 10 DATA5,EMAD5,GPIO5 9 DATA6,EMAD6,GPIO6 8 DATA7,EMAD7,GPIO7 7 A0,SCCLK RAM PROGRAM MEMORY RAM DATA MEMORY RAM OUTPUT BUFFER OUTPUT FORMATTER HOST INTERFACE 24-Bit DSP PROCESSING 39 40 41 42 43 44 12 3 4 5 6

RESET DD DC

36 37 38

STC

ROM PROGRAM MEMORY ROM DATA MEMORY

RD, INTREQ

LRCLK SCLK MCLK CMPCLK,

EMWR, GPIO8 ABOOT,

PLL CIRCUIT

VDD1

WR,

AUDATA1 AUDATA0

â 57 â

A1,

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