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Pin Name MODE2 MODE1 HST HCK1 HCK2 BLK CLR ENB VCK VST VSS TST7 PCG TST8 DWN RSTR RCK RSTW WCK VSS VDD XCLR PRE TST9, TST10 FLDI FLDO HD
I/O O O O O O O O O O O � I O I O O O O O � � I I I I O O
Function Mode changes signal output to the L & R LCD units Mode changes signal output to the L & R LCD units Horizontal start pulse output to the L & R LCD units Horizontal clock 1 pulse output to the L & R LCD units Horizontal clock 2 pulse output to the L & R LCD units Blanking pulse output to the L & R LCD units (positive polarity) Clear pulse output to the L & R LCD units (positive polarity) Enable pulse output to the L & R LCD units (negative polarity) Vertical clock pulse output to the L & R LCD units Vertical start pulse output to the L & R LCD units Ground terminal Input terminal for the test Not used (open) PCG pulse output to the gamma control IC (IC201) and L & R LCD units (positive polarity) Input terminal for the test Not used (open) Up-down inversion distinguishing signal output to the L & R LCD units �L�: up, �H�: down Reset read signal output to the line memory (IC1104 to 1106) (for high speed line buffer/negative polarity) Read clock signal output to the video RGB A/D converter (IC1101 to 1103), line memory (IC1104 to 1106) and video RGB D/A converter (IC1201) (for high speed line buffer) Reset write signal output to the line memory (IC1104 to 1106) (for high speed line buffer/negative polarity) Write clock signal output to the video RGB A/D converter (IC1101 to 1103) and line memory (IC1104 to 1106) (for high speed line buffer) Ground terminal Power supply terminal (+5V) System clear signal input from the system controller (IC501) �L�: all clear Input terminal for the presetting (�L�: preset to Macintosh 16 mode) Fixed at �H� in this set Input terminal for the test Not used (open) Field distinguishing signal input terminal In this set, the signal from FLDO &ª pin is input Field distinguishing signal output terminal Horizontal drive pulse output terminal (positive polarity)
